Exploring the design space of signed-binary adder cells.

Abstract

Arithmetic based on signed-binary number representation is an alternative to carry-save arithmetic. Both offer adders with word-length independent latencies. Comparing both approaches requires optimized adder cells. Small and fast full adder designs have been introduced. A thorough investigation of signed-binary adder cells is still missing. We show that for an example signed-binary encoding scheme the design space consists of 2^38 different truth tables. Each represents a bit-level signed-binary adder cell. We proposed a new method to enumerate and analyze such a huge design space to gain small area, low power, or low latency signed-binary adder cells and show the limitations of our approach.