Design and Evaluation of Computer Arithmetic Based on Carry-Save and Signed-Digit Redundant Number Representation.

Abstract

The continuing demand for technological advances while dealing with mutual constraining characteristics of digital systems as for instance lowe r feature size, lower power consumption, and lower compute latency drives a need for constant innovation. To further improve state-of-the-art digital hardware, thorough knowledge of computer arithmetic is needed. This thesis explores select ed aspects of the design and evaluation of computer arithmetic based on carry-sa ve and signed-digit redundant number representations to reduce the area, the cri tical path latency, and the power consumption of arithmetic circuits. Carry-save arithmetic is frequently used to realize basic arithmetic operations requiring inner product calculations, as multiplication, multiply-add, multiply-accumulate , and digital filters. This thesis enhances multiplication and multiply-accumula tion based on carry-save arithmetic by improving the well known Wallace and Dadd a partial product reduction strategies. An alternative concept of time-based red uction strategies is introduced as well and applied to multiply-accumulate units resulting in reduced area, critical path latency, and power consumption. A comp etitive redundant number representation is the signed-digit number representatio n. Not frequently implemented in state-of-the-art hardware designs, it is recurr ing in prototype development. Implemented signed-digit arithmetic is based on si gned-binary adder cells. This thesis demonstrates the need for optimizing these cells and presents concepts of a systematic design space exploration of signed-b inary adder cells. Additionally, the error resilience capabilities of signed-dig it arithmetic is evaluated and favorable digit encoding schemes are presented.